The present invention generally relates to a color television set. More particularly, the present invention relates to an automatic cut-off system for adjusting the balance of primary-color signals of red (R), green (G) and blue (B) which are applied to a CRT (cathode-ray tube).
Recent color television sets automatically maintain the same current ratio of cathodes of R, G, B as before shipment in order to prevent variation in white balance from being caused by aging of a CRT and drive circuitry. In particular, a system for conducting control so that the black level of each primary-color signal of R, G, B corresponds to a cut-off voltage of the CRT is called an automatic cut-off system.
FIG. 6 is a block diagram of a conventional automatic cut-off system. For simplicity, FIG. 6 shows only circuitry for one of the primary-color signals of R, G, B. A cathode current of a CRT 83 flows through a resistor 84, and a voltage proportional to the cathode current is generated at the resistor 84. A cut-off level detector 92 receives this voltage as a feedback voltage FB0 and outputs the level of the feedback voltage FB0 to a sample-and-hold circuit 93.
A video data processing circuit 81 receives a digitized video signal, a vertical synchronization signal VS and a horizontal synchronization signal HS. The video data processing circuit 81 adds a cut-off reference pulse having a level corresponding to the black level to each of the three primary-color signals of R, G, B and outputs the resultant primary-color signals to a digital-to-analog (D/A) converter 82. The video data processing circuit 81 generates a vertical blanking pulse and a horizontal blanking pulse for output to a logic operation circuit 91. The logic operation circuit 91 generates a timing pulse for sample-and-hold operation based on the vertical blanking pulse and the horizontal blanking pulse, and outputs the timing pulse to the sample-and-hold circuit 93. This timing pulse indicates the timing of the cut-off reference pulse.
The sample-and-hold circuit 93 obtains a current according to the subtraction result of the feedback voltage FB0 from a predetermined reference voltage and applies the current thus obtained to a capacitor for sample-and-hold operation (hereinafter, referred to as sample-and-hold capacitor) 85 within a period of the received timing pulse. In other words, the sample-and-hold capacitor 85 is charged if the feedback voltage FB0 is lower than the reference voltage, and discharged when the feedback voltage FB0 is higher than the reference voltage. The sample-and-hold circuit 93 outputs the voltage of the sample-and-hold capacitor 85 to a cut-off control circuit 95 as a cut-off control voltage.
The D/A converter 82 converts a received signal to an analog signal. The analog signal is applied to the cut-off control circuit 95 through an amplifier 94. The cut-off control circuit 95 conducts cut-off control of the received primary-color signal according to the cut-off control voltage. In other words, the cut-off control circuit 95 shifts the level of the received primary-color signal according to the cut-off control voltage. The cut-off control circuit 95 outputs the resultant primary-color signal to the CRT 83 and drives a corresponding cathode.
FIG. 7 is a waveform chart showing an example of signal waveforms in the circuitry of FIG. 6. The feedback voltage FB0 has pulses according to the cut-off reference pulses in a vertical blanking interval. For simplicity, FIG. 7 shows the level of the tip of the pulses. When a low voltage corresponding to the black level is applied to the CRT 83, a cathode current is small and the feedback voltage FB0 is also small. Since the feedback voltage FB0 detected in the period of the timing pulse for sample-and-hold operation is lower than the reference voltage, the sample-and-hold capacitor 85 is charged in the period of the timing pulse to raise the voltage of the sample-and-hold capacitor 85. This raises the cut-off control voltage and the voltage of the black level. As the voltage of the black level rises, the detected feedback voltage FB0 also rises.
When the feedback voltage FB0 exceeds the reference voltage, the sample-and-hold capacitor 85 is discharged in the period of the timing pulse for sample-and-hold operation to reduce the voltage of the sample-and-hold capacitor 85. This reduces the voltage of the black level. Finally, the detected feedback voltage FB0 becomes equal to the reference voltage, and cut-off control reaches a steady state.
Cut-off control can be conducted automatically by controlling three primary-color signals of R, G, B in the same manner by using the same circuitry as that of FIG. 6.
In the circuit having the above structure, however, it takes a long time to charge the sample-and-hold capacitor 85. Accordingly, white balance cannot be obtained during a period of several hundreds of fields from power-on until the cut-off control reaches a steady state. As a result, an image cannot be displayed in normal colors during this period.
In order to reduce the time required to charge the sample-and-hold capacitor 85, it is necessary to reduce the capacity of the sample-and-hold capacitor 85 and increase a charging current. However, a greater capacity would be better in view of leakage of a current. Moreover, excessively high sensitivity of automatic regulation would destabilize control. Therefore, the charging current cannot be increased so much. This makes it difficult to reduce the time required to charge the sample-and-hold capacitor 85.